? semiconductor components industries, llc, 2002 june, 2002 rev. 5 1 publication order number: mc100lvel91/d mc100lvel91 3.3v / 5vtriple lvpecl / pecl input to -3.3v ecl output translator the mc100lvel91 is a triple lvpecl / pecl input to ecl output translator. the device receives standard or low voltage differential pecl signals, determined by the v cc supply level, and translates them to differential 3.3 v ecl output signals. (for translation to 5 v ecl output, see mc100el91.) to accomplish the level translation the lvel91 requires three power rails. the v cc supply should be connected to the positive supply, and the v ee pin should be connected to the negative power supply. the gnd pins are connected to the system ground plane. both v ee and v cc should be bypassed to ground via 0.01 f capacitors. under open input conditions, the d input will be biased at v cc /2 and the d input will be pulled to gnd. this condition will force the q output to a low, ensuring stability. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. ? 620 ps typical propagation delay ? the 100 series contains temperature compensation ? operating range: v cc = 3.0 v to 5.25 v; v ee = 3.0 v to 3.8 v; gnd= 0 v ? q output will default low with inputs open or at gnd marking diagram* a = assembly location wl = wafer lot yy = year ww = work week so20 dw suffix case 751d 1 20 device package shipping ordering information mc100lvel91dw so20 38 units/rail mc100lvel91dwr2 so20 1000 units/reel *for additional information, see application note and8002/d http://onsemi.com 1 20 mc100lvel91 awlyyww
mc100lvel91 http://onsemi.com 2 ecl ecl ecl figure 1. 20lead pinout (top view) and logic diagram 17 18 16 15 14 13 12 4 3 5678 9 11 10 19 20 2 1 pin description function pecl/lvpecl inputs ecl outputs pecl reference voltage output positive supply negative supply ground pin dn, dn qn, qn pecl v bb v cc v ee gnd warning: all v cc , v ee , and gnd pins must be externally connected to power supply to guarantee proper operation. pecl/ lvpecl pecl/ lvpecl pecl/ lvpecl * all v cc pins are tied together on the die. pecl v bb pecl v bb v cc d0 d0 d1 d1 d2 d2 v ee gnd gnd v cc q0 q0 q1 q1 q2 q2 v cc attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 75 k esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index: 28 to 34 ul 94 v0 @ 0.125 in transistor count 282 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl power supply gnd = 0 v 8 to 0 v v ee necl power supply gnd = 0 v 8 to 0 v v i pecl input voltage gnd = 0 v v i v cc 6 to 0 v i out output current continuous surge 50 100 ma ma i bb pecl v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 20 soic 20 soic 90 60 c/w c/w q jc thermal resistance (junction to case) std bd 20 soic 30 to 35 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur.
mc100lvel91 http://onsemi.com 3 lvpecl input dc characteristics v cc = 3.3 v; v ee = 3.3 v; gnd = 0 v (note 3) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i cc v cc power supply current 11 6 11 11 ma v ih input high voltage (singleended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (singleended) 1490 1825 1490 1825 1490 1825 mv lvpecl v bb output voltage reference 1.92 2.04 1.92 2.04 1.92 2.04 v v ihcmr input high voltage common mode range (differential) (note 4) vpp < 500 mv vpp 500 mv 1.0 1.2 2.9 2.9 0.9 1.1 2.9 2.9 0.9 1.1 2.9 2.9 v v i ih input high current 150 150 150 m a i il input low current d d 0.5 600 0.5 600 0.5 600 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. input parameters vary 1:1 with v cc . v cc can vary +0.5 / 0.3 v. 4. v ihcmr min varies 1:1 with gnd. v ihcmr max varies 1:1 with v cc . pecl input dc characteristics v cc = 5.0 v; v ee = 3.3 v; gnd = 0 v (note 5) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i cc v cc power supply current 11 6 11 11 ma v ih input high voltage (singleended) 3835 4120 3835 4120 3835 4120 mv v il input low voltage (singleended) 3190 3525 3190 3525 3190 3525 mv pecl v bb output voltage reference 3.62 3.74 3.62 3.74 3.62 3.74 v v ihcmr input high voltage common mode range (differential) (note 6) vpp < 500 mv vpp 500 mv 1.0 1.2 4.6 4.6 0.9 1.1 4.6 4.6 0.9 1.1 4.6 4.6 v i ih input high current 150 150 150 m a i il input low current d d 0.5 600 0.5 600 0.5 600 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 5. input parameters vary 1:1 with v cc . v cc can vary 0.25 v. 6. v ihcmr min varies 1:1 with gnd. v ihcmr max varies 1:1 with v cc . necl output dc characteristics v cc = 3.3 v to 5.0 v; v ee = 3.3 v; gnd = 0 v (note 7) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee v ee power supply current 27 21 27 29 ma v oh output high voltage (note 8) 1085 1005 880 1025 955 880 1025 955 880 mv v ol output low voltage (note 8) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mv note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 7. output parameters vary 1:1 with gnd. v ee can vary +0.3 v / 0.5 v. 8. all loading with 50 ohm resistor to gnd2 volts.
mc100lvel91 http://onsemi.com 4 ac characteristics v cc = 3.0 v to 5.5 v; v ee = 3.0 v to 3.8 v; gnd = 0 v 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit fmax maximum toggle frequency 600 600 600 mhz t plh t phl propagation delay differential d to q selectended 490 440 590 590 690 740 520 470 620 620 720 770 560 510 660 660 760 810 ps t skew skew outputtooutput (note 9) parttopart (differential) (note 9) duty cycle (differential) (note 10) 40 25 100 200 40 25 100 200 40 25 100 200 ps v pp input swing (note 11) 200 1000 200 1000 200 1000 mv t r t f output rise/fall times q (20% 80%) 320 400 580 320 400 580 320 400 580 ps 9. skews are valid across specified voltage range, parttopart skew is for a given temperature. 10. duty cycle skew is the difference between a t plh and t phl propagation delay through a device. 11. v pp (min) is the minimum input swing for which ac parameters are guaranteed. the device has a dc gain of 40. figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d v tt = gnd 2.0 v
mc100lvel91 http://onsemi.com 5 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc100lvel91 http://onsemi.com 6 package dimensions so20 dw suffix plastic soic package case 751d05 issue f 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc100lvel91 http://onsemi.com 7 notes
mc100lvel91 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100lvel91/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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